岗位职责:
-Work closely with process RD team to develop DRC/LVS for design readiness.
-Provide customer support to world-wide leading design house.
-Initial more innovation to continue optimize development efficiency.
-Work closely with various departments (Physical design/integration/Device RD/Product/ESD) on their design requirements.
-Work closely with EDA partner for tool qualification and methodology enhance.
任职要求:
-Good knowledge of semiconductor FEOL/BEOL process and chip design concepts. Solid understanding of device physics, Layout design is a plus.
-Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus. Especially Laker /Virtuoso /Calibre.
-ｓｃｒｉｐｔing and programming experience using several of the following: Perl, Python, C, C++, TCL, Skill.
-Ability to work across teams to drive a solution, problem solver and self-motivated.
-The ideal candidate will have experience in DRC/LVS development.
-MS or above in EE, CS related fields.

TSMC 暑期实习 - 2023 DNA 积因计划

申请实习，你也有机会拿到加入台积电的入场券！

TSMC DNA积因计划将提供你/妳：
1. 扎实的 ON JOB TRAINING
2. 丰富的课程深入认识半导体产业
3. 实务项目熟悉台积企业文化与工作模式

最重要的是~ 表现优秀的应届毕业生
就有机会获得台积预聘offer！

招募对象：大三以上同学为主，含研究生

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