岗位职责:
-Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)
-Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective)
任职要求:
-Good knowledge of circuits design. Experience in digital circuit or analog design is preferred.
-Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred
-CAD and ｓｃｒｉｐｔ capability such as Python/Perl/Shell is preferred.
-Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.
-Experience in reliability (EM, high-temperature aging effects, etc.) is a plus
-Self-motivated and hard work.

TSMC 暑期实习 - 2023 DNA 积因计划

申请实习，你也有机会拿到加入台积电的入场券！

TSMC DNA积因计划将提供你/妳：
1. 扎实的 ON JOB TRAINING
2. 丰富的课程深入认识半导体产业
3. 实务项目熟悉台积企业文化与工作模式

最重要的是~ 表现优秀的应届毕业生
就有机会获得台积预聘offer！

招募对象：大三以上同学为主，含研究生

欢迎志同道合的伙伴，一起加入台积
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专业要求：不限