岗位职责:
-Full layout design for standard cell/IO/SRAM IPs in advanced process nodes
-Work on the physical verification (DRC/LVS/Antenna ...)
-Work on test chip layout design and verification
-Close cooperation with designers on PPA optimization
任职要求:
-At least BS Degree of Microelectronics or Physics.
-Excellent graduate or at least 1 years＇ related working experience
-Familiar with layout design and verification tools (Virtuoso, Laker, Calibre)
-Familiar with design rule and layout effect in advanced process.
-Excellent skills of communication and teamwork are also expected.
-Programming experience (Perl/tcl skill) will be a plus.
-Experience in advanced process (n16 and beyond) will be a plus.

TSMC 暑期实习 - 2023 DNA 积因计划

申请实习，你也有机会拿到加入台积电的入场券！

TSMC DNA积因计划将提供你/妳：
1. 扎实的 ON JOB TRAINING
2. 丰富的课程深入认识半导体产业
3. 实务项目熟悉台积企业文化与工作模式

最重要的是~ 表现优秀的应届毕业生
就有机会获得台积预聘offer！

招募对象：大三以上同学为主，含研究生

欢迎志同道合的伙伴，一起加入台积
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专业要求：不限