Position: Analog Layout Design Engineer
Location: Shanghai
Position Deｓｃｒｉｐｔion:
Skillful capable of AMS layout Design area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc.
Proficient with Cadence layout tools specifically Virtuoso XL and Assura (Version ICADVM experience is a plus)
Ability to coordinate with the other analog IC circuit layout, ensuring robust, efficient, consistent and successful ｄｅｌivery of analog IC circuit layout.
Fundamental understanding of IC design technology and process/methodology (TSMC or Samsung FINFET experience is a plus)
Skilled in Analog IC top level chip assembly including floor planning and block layout
Hands-on experience conducting DRC/LVS analysis and recommending appropriate solutions (EMIR fix experience is a plus)
Qualifications:
BSEE degree with 1+ years of applicable experience in analog design industry
Essential that the individual demonstrates strong communication, verbal and written, and project management skills
Requires good communication skills in English and Chinese

上班地址：-上海-东育路221弄1号前滩世贸中心